1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device and a driving unit thereof, and particularly, to a liquid crystal display (LCD) device and driving unit capable of facilitating application of high resolution and improving image quality.
2. Description of the Background Art
Recently, since information was visually embodied, display devices which act as an interface between human being and information have been widely utilized. More particularly, because of the superior characteristics of liquid crystal display (LCD) devices such as clear image quality, low power consumption, light weight and the like, the LCD devices have been gradually utilized as a next-generation display device which can substitute for widely used Cathode Ray Tubes (CRTs).
FIG. 1 schematically illustrates a typical liquid crystal display device. As illustrated in FIG. 1, a LCD device includes a liquid crystal display (LCD) panel 1 formed by attaching a thin film transistor array substrate 2 and a color filter substrate 3 to each other with a constant cell-gap, a plurality of data lines 15 and gate lines 16 arranged perpendicularly and longitudinally on the thin film transistor array substrate 2, a plurality of pixels P defined by crossing the data lines 15 and the gate lines 16, a data driving unit 20 for transferring image information to the pixels P through the data lines 15, and a gate driving unit 30 for applying scan signals to the pixels P through the gate lines 16.
The thin film transistor array substrate 2 on which the pixels P are arranged in a matrix has an image display unit 10 composed of the pixels P, for substantially displaying images thereon.
The data driving unit 20 is electrically connected to the image display unit 10 by the data lines 15, while the gate driving unit 30 is electrically connected to the image display unit 10 by the gate lines 30. The gate lines 16 and the data lines 15 are respectively electrically connected to the pixels P to form the image display unit 10.
The gate driving unit 30 sequentially outputs scan signals to the gate lines 16 and applies the scan signals to the pixels P connected to the gate lines 16. Thin film transistors TFTs provided to each pixel P are turned on by the scan signals. During this period for turning on the TFTs, the data driving unit 20 applies image information, i.e., data signals, to the pixels P through the turned-on TFTs.
The pixels P are provided therein with storage capacitors, by which a voltage of the image information, which has been applied to the pixels P when the TFTs are turned on by the scan signals, is charged to keep driving the pixels P for one frame when the TFTs are in an off state.
A plurality of driving voltages and control signals are inputted to the gate driving unit 30, which is then controlled by the control signals to sequentially output scan signals to the gate lines 16. As will be explained in FIG. 2A, the gate driving unit 30 is provided with a shift register unit for sequentially generating signals every horizontal period to thereby output the scan signals in sequence.
FIG. 2A illustrates the shift register unit of the gate driving unit 30, and FIG. 2B shows the timing sequences of the signals shown in FIG. 2A. The shift register unit is driven by inputting a gate start voltage Vst, and is provided with a plurality of stages ST1 to STn for outputting scan signals Vout1 to Voutn according to a plurality of clock signals C1 to C4.
Four clock lines CL1 to CL4 are provided at one side of the shift register unit. The stages ST1 to STn are electrically connected to one of the four clock lines CL1 to CL4. A high potential voltage Vdd and a low potential voltage Vss are commonly applied to the stages ST1 to STn. The shift register unit may only use two clock lines CL1 and CL2.
An output side of each of the stages ST1 to STn is electrically connected to its next preceding stage as wells as to its next subsequent stage. Although not shown, each of the stages ST1 to STn has one-to-one connection with its respective gate line.
The stages ST1 to STn are preset by the gate start voltage Vst to be in a state of immediately outputting the scan signals Vout1 to Voutn by inputting the clock signals C1 to C4. The gate start voltage Vst is inputted only to the first stage ST1 and outputted to a timing controller. In each of the other stages ST2 to STn, the scan signals Vout1 to Voutn−1 of the next preceding stages ST1 to STn−1 perform a function as same as that of the gate start voltage Vst. That is, the scan signals Vout1 to Voun−1 of the next preceding stages ST1 to STn−1 are inputted to the next subsequent stages ST2 to STn to preset the corresponding stages ST2 to STn. Accordingly the corresponding stages ST2 to STn are synchronized with the clock signals C1 to C4 to be in a state that the scan signals Vout2 to Voutn can immediately be outputted.
On the other hand, each of the scan signals Vout2 to Voutn is applied to the next preceding stages ST1 to STn−1 to stop the output of the next preceding stages ST1 to STn−1. In addition, the scan signals Vout1 to Voutn are outputted to only one of the stages ST1 to STn.
FIG. 2B illustrates the timing sequences of the clock signals C1 to C4 applied to the shift register unit and of the scan signals Vout1 to Voutn controlled by the clock signals C1 to C4. When the gate start voltage Vst is firstly inputted and the clock signals C1 to C4 are then sequentially inputted to the stages ST1 to STn, the scan signals Vout1 to Voutn are sequentially outputted from the stages ST1 to STn. The scan signals Vout1 to Voutn are generated every horizontal period H.
FIG. 3 illustrates an exemplary circuit configuration of the shift register unit shown in FIG. 2A. As illustrated in the drawing, the shift register unit is provided with a plurality of flip-flops FF1 to FF3 for outputting the scan signals Vout1 to Vout3 by inputting the clock signals C1 to C3 in a state that the gate start voltage Vst has been applied thereto. Each output side of the flip-flops FF1 to FF3 has one-to-one connection with the gate lines GL1 to GL3 arranged on a substrate in a lateral direction.
Each of the flip-flops FF1 to FF3 includes: a second transistor T2 turned on by a high potential voltage Vdd, for charging a second Node ND2; a first transistor T1 turned on/off by the gate start voltage Vst, for discharging the second Node ND2 and for charging a first Node ND1; a seventh transistor T7 electrically connected to one side of the charged first Node ND1 and turned on/off by a voltage charged in the first Node ND1, for outputting scan signals Vout1 to Voutn according to clock signals C1 to C4; a fourth transistor T4 turned on/off by signals outputted from a next subsequent flip-flop, for discharging the first Node ND1 and recharging the second Node ND2, and an eighth transistor T8 turned on/off by a voltage charged in the second Node ND2, for lowering the voltage level of the scan signals Vout1 to Voutn to a low potential voltage. The first to eighth transistors T1 to T8 are all N-type.
The first Node ND1 electrically connects a source electrode of the first transistor T1, a gate electrode of the seventh transistor T7 and a drain electrode of the fourth transistor T4. The second Node ND2 electrically connects a source electrode of the second transistor T2 and gate electrodes of the eighth and third transistors T8 and T3.
The output of the flip-flops FF1 to FF3 is controlled by potentials of the first Node ND1 and the second Node ND2. That is, when the first Node ND1 is in a high potential, the seventh transistor T7 is turned on to transit the scan signals Vout1 to Vout3 into high potential levels, while transiting the scan signals Vout1 to Vout3 into low potential levels when the eighth transistor T8 is turned on.
The scan signals Vout1 to Vout3 of the flip-flops FF1 to FF3 are supplied to the gate lines GL1 to GL3 and simultaneously applied to the next subsequent flip-flops FF2 to FF4 (not shown) to thereby perform a function as same as that of the gate start voltage Vst applied to the first flip-flop FF1. That is, the first transistor T1 of the current flip-flops FF1 to FF3 is turned on to charge the first Node ND1. Furthermore, the scan signals of the flip-flop FF2 to FF4 are transferred to the next preceding flip-flops FF1 to FF3 to discharge the first Node ND1 of the next preceding flip-flops FF1 to FF3. If the first Node ND1 of the next preceding flip-flops FF1 to FF3 is not completely discharged, when the current flip-flops output scan signals, minute signals can still be outputted from the next preceding flip-flops. In other words, an abnormal output of the scan signals of the next preceding flip-flops FF1 to FF3 can be prevented by completely discharging the first Node ND1. Thus, the scan signals of the current flip-flops control the output of both the next preceding and the next subsequent flip-flops.
Recently, LCD devices with large dimension and high resolution have been developed. In order to make the devices lighter, a driving unit which has been installed in a LCD panel as IC chip (Integrated Circuit Chip) type is integrated with the LCD panel. Thus, the driving circuit integrated with the LCD panel is generally formed of amorphous silicon transistor.
On the other hand, because the number of pixels is increased to enhance the resolution of screen, the number of the gate lines is also increased to control the increased pixels. Accordingly, more flip-flops should be formed corresponding to the increased number of gate lines. Since the number of the gate lines is increased, the scanning frequency has to be increased. In other words, a horizontal period for applying scan signals to each gate line for one frame is reduced.
When the horizontal period for applying scan signals to each gate line is reduced, a time assigned to each flip-flop for outputting scan signals is also reduced. Therefore, it would be difficult to ensure a sufficient time for charging the first Node ND1. In the state that the first Node ND1 is not enough charged, a gate voltage for turning on the seventh transistor T7 is lowered, and accordingly current flowing through the seventh transistor T7 is also reduced. As a result, potential levels of the scan signals rise at a lower speed, which requires a longer time period (rising time) to raise the scan signals up to high potential levels. That is, pulses of the scan signals fall with delay.
Similarly, when the horizontal period is reduced, it is difficult to ensure a sufficient time taken by charging the second Node ND2. As a result, the eighth transistor T8 is not completely turned on, which causes limitation on electric charge which is discharged through the eighth transistor T8, thereby taking a longer time period (falling time) to lower the potential levels of the scan signals. Furthermore, resistance and capacitance elements of the increased gate lines increase a load in the shift register unit to lengthen the rising time and the falling time of the scan signals. That is, pulses of the scan signals Vout1 to Vout3 fall with delay.
Thus, when the pulses of the scan signals Vout1 to Vout3 fall with delay by the incomplete charging of the first Node ND1 and the second Node ND2, each flip-flop outputs the scan signal which does not have desired potential level for the gate line. Accordingly, when the scan signals are applied to the gate lines, image quality of the LCD device may be degraded. Especially, in the driving circuit-integrated LCD panel applying amorphous silicon transistor thereto, due to its lower electron mobility, the rising time and the falling time of the scan signals may be longer.
Moreover, when the rising time or the falling time of the scan signals is lengthened, waveforms of the scan signals fall with delay to maintain high potential levels for a long time, thereby unnecessarily turning on TFTs. In this case, image information may be applied to pixels through the TFTs which should have been turned off. This may cause degradation of image quality. In addition, when the waveforms of the scan signals fall with delay, the time period for outputting the scan signals have to be further reduced to prevent adjacent scan signals from being overlapped with one another, which makes it difficult to fabricate a LCD device with high resolution.